1. Field of the Invention
The present invention relates to a driver and a TFT type liquid crystal display apparatus using the driver to display a display data.
2. Description of Related Art
A TFT type liquid crystal display apparatus has become popular. FIG. 1 shows a configuration of the conventional TFT type liquid crystal display apparatus. The TFT type liquid crystal display apparatus contains a display panel (liquid crystal panel) 140, a gate driver (not shown), a source driver 101 and a power source circuit 130.
The liquid crystal panel 140 contains a plurality of pixels 143 that are arranged in a matrix. Each of the plurality of pixels 143 contains a thin film transistor (TFT) and a pixel capacitor. The pixel capacitor contains a pixel electrode and a counter electrode opposing to the pixel electrode. The TFT contains a drain electrode, a source electrode connected to the pixel electrode, and a gate electrode.
The liquid crystal panel 140 further contains a plurality of gate lines 142 and a plurality of data lines 141. Each of the plurality of gate lines 142 is connected to the gate electrodes of the TFTs of the pixels 143 on one row. Each of the plurality of data lines 141 is connected to the drain electrodes of the TFTs of the pixels 143 on one column.
The power source circuit 130 contains gradation resistor elements that are connected in series. In the power source circuit 130, a reference voltage is divided by the gradation resistor elements, to generate a plurality of gradation voltages.
In one horizontal period, it is assumed that the gate driver sequentially selects one gate line 142 from the plurality of gate lines 142 from the first gate line to the last gate line in response to the signal. In this case, a selection signal is outputted from the gate driver to the gate line 142 and the TFTs of the pixels 143 on the selected gate line 142 are turned on. This is similarly applied to the other gate lines 142.
A display data for one screen (one frame) corresponding to the plurality of data lines 141 from the first line to the last line and a clock signal CLK are supplied to the source driver 101. The source driver 101 selects one gradation voltage from the plurality of gradation voltages based on the display data in synchronization with the clock signal CLK, and outputs the selected gradation voltage to a corresponding data line of the plurality of data lines 141. At this time, the TFT of a selected pixel 143 connected with the corresponding gate line 142 and the corresponding data line 141 is turned on. For this reason, the gradation voltage is written into the pixel capacitor of the selected pixel 143 and held until a next write timing. Thus, the display data for one line is displayed.
In the TFT type liquid crystal display apparatus, usually, each dot of the image is composed of three pixels corresponding to the basic primary colors of red, green and blue. For example, three switches are respectively provided for the pixels of R, G and B, with respect one output of the source driver. In the TFT type liquid crystal display apparatus, the three switches are switched at a constant time interval, to allow one amplifier to drive to the three pixels. This method is called as a 3-time-divisional drive, and is described in, for example, Japanese Publication (JP 2003-208132A).
In the TFT type liquid crystal display apparatus, usually, the pixels for one line scanned or selected by the gate driver must be driven within one horizontal period (scanning period 1H). Thus, when the time divisional drive is executed, switching of the switches must be executed between the horizontal period 1H.
By the way, a driver for a mobile terminal has become popular as the source driver of the TFT type liquid crystal display apparatus. Here, a technique to drive 6 pixels, 9 pixels, or 12 pixels by one output of the driver is required. In such a driver, naturally, each pixel needs to be driven at the time of 1H/6, 1H/9 or 1H/12 by increasing the number of time divisions.
A case in which the 6-time-divisional drive is performed in the configuration of the TFT type liquid crystal display apparatus described in Japanese Publication (JP 2003-208132A), namely, a case of driving six pixels (two dots) will be described with reference to FIGS. 1 and 2. FIG. 2 shows timing charts in the configuration shown in FIG. 1.
The driver 101 contains six latching sections 111, six input switches SW1 to SW6 112, a D/A converter DAC 113, an amplifier 114 and a controller 120. The liquid crystal panel 140 contains six data line switches SWp1 to SWp6 144. The six latching sections 111 latch supplied display data DATAm1 to DATAm2 151, respectively. The input switches SW1 to SW6 112 are connected to the outputs of the latching sections 111, respectively. Each of the input switches SWj 112 (j=1, 2, . . . , 6) is turned on in response to an input switching control signal ENj 121.
The D/A converter 113 is connected to the input switches SW1 to SW6 112 and converts the display data DATAmj 151 from the latching section 111 connected to the input switch SWj 112 into an output gradation voltage DAOUTm 152. The amplifier 114 is connected to the D/A converter 113 and an output node OUTm. The amplifier 114 outputs the output gradation voltage DAOUTm 152 outputted from the D/A converter 113 to the output node OUTm.
Data lines SOm1 to SOm6 141 on the liquid crystal panel 140 are connected to the output node OUTm through the data line switches SWp1 to SWp6 144, respectively. A data line switch SWpj 144 among the data line switches SWp1 to SWp6 144 is turned on in response to a data line switching control signal OENj 123.
The controller 120 is connected to the input switches SW1 to SW6 112 and the data line switches SWp1 to SWp6 144. The controller 120 supplies first to sixth input switching control signals EN1 to EN6 121 to the input switches SW1 to SW6 112, respectively. Also, the controller 120 supplies first to sixth data line switching control signals OEN1 to OEN6 123 to the six data line switches SWp1 to SWp6 144 in synchronization with the input switching control signals EN1 to EN6 121, respectively.
Usually, one horizontal period (1H) is a time period obtained by dividing a time period required to rewrite data for one screen (and corresponding to a frame frequency) by the number of scans (the number of display lines). In the TFT type liquid crystal display apparatus, even if the number of time divisions is increased, the frame frequency cannot be made low in order to avoid an influence of flicker. That is, the horizontal period cannot be increased in accordance with the increase the number of time divisions. For this reason, when the number of time divisions is increased in order to decrease a chip area, for example, when an M-time division (M is a multiple of 3) is executed, the time when one source driver drives the M pixels is required to be 1H/M or less. Oppositely, unless one pixel can be driven within this time, a time longer than the horizontal period is required in the M-time division drive. Thus, the pixel on a next line cannot be driven.
Thus, as the time period during which one pixel is driven is reduced to 1H/3, 1H/6, 1H/12 . . . , the high-speed drive becomes absolutely imperative. However, in order to make the time period shorter, the settling time of the output of the D/A Converter 113 serving as the input of the amplifier 114 is required to be made shorter, and a through rate of the amplifier 114 is required to be increased and the settling time of the amplifier 114 is required to be made shorter.
In the TFT type liquid crystal display apparatus, when a 6-time-divisional drive is performed, the display data DATAm1 to DATAm6 151 are sequentially selected in synchronization with the input switching control signals EN1 to EN6 and outputted as the output gradation voltages DAOUT1 to DAOUT6 to the data lines SOm1 to SOm6 141. In the source driver 101, a time period from a time when the D/A converter 113 inputs the display data DATAmj 151 based on the input switching control signal ENj to a time when the D/A converter 113 selects and outputs the output gradation voltage DAOUTj 152 from the plurality of gradation voltages generated by the power source circuit 130 based on the display data DATAmj 151 is defined as a D/A converter delay time (Td_DA). Also, a time period from a time when the amplifier 114 inputs the output gradation voltage DAOUTj 152 to a time when the output of the amplifier 114 is stabilized (determined) is defined as an amplifier settling time (Td_Amp). In this case, a time period from the time when the display data DATAmj 151 is selected in response to the input switching control signal ENj to the time when the output gradation voltage DAOUTj 152 is outputted from the amplifier 114 is determined by a sum of the D/A converter delay time (Td_DA) and the amplifier settling time (Td_Amp).
The D/A converter delay time (Td_DA) is a delay, which is proportional to a CR time constant determined based on output impedance and parasitic load of the power source circuit 130 and a CR time constant determined based on ON resistance and parasitic capacitance of a transistor configuring the D/A converter 113. Thus, in the TFT type liquid crystal display apparatus, in order to simply reduce the D/A converter delay time (Td_DA) to ½, it is required that a total resistance (Rall) of the gradation resistors in the power source circuit 130 is reduced to ½, and the number of transistors switches in the D/A converter is doubled, so that the on resistance is reduced to ½. However, in this case, the current flowing through the gradation resistors inside the power source circuit 130 becomes double. Also, since the number of transistor switches inside the D/A converter becomes double, the layout size is also doubled. Also, in the TFT type liquid crystal display apparatus, in order to decrease the through rate and output impedance of the amplifier 114 with respect to the settling delay of the amplifier 114, it is required that a bias current is doubled and the transistor size at the output stage of the amplifier 114 is doubled.